1. Field of the Invention
The present invention relates in general to pulse width modulation apparatus for modulating input signals to electronic appliances into pulse signals or digital signals, and more particularly to a pulse width modulation apparatus in which the processing speed is enhanced and the construction is simplified so that the integration can be enhanced in manufacturing a single chip.
2. Description of the Prior Art
Referring to FIG. 1, there is shown a functional block diagram of a conventional pulse width modulation apparatus. As shown in this drawing, the conventional pulse width modulation apparatus comprises a register 1 for temporarily storing purse width data D0-D3 inputted over a data bus, a counting controller 2 for controlling output of a clock signal CK inputted therein in response to an external pulse width modulation enable signal PE, and a counter 3 for counting the clock signal CK outputted from the counting controller 2 in response to an external reset signal RE.
A comparison circuit 4 is provided in the conventional pulse width modulation apparatus to compare the pulse width data D0-D3 from the register 1 with data Q0-Q3 from the counter 3 and output a high signal when the data Q0-Q3 from the counter 3 is greater than the pulse width data D0-D3 from the register 1 and a low signal when the data Q0-Q3 from the counter 3 is not greater than the pulse width data D0-D3 from the register 1.
An output unit 5 is also provided in the conventional pulse width modulation apparatus to latch an output signal from the comparison circuit 4, so as to output a pulse width modulation signal PWMO.
The operation of the conventional pulse width modulation apparatus with the above-mentioned construction will hereinafter be described with reference to FIG. 1 and FIGS. 2A to 2F which are waveform diagrams of the signals from the components in FIG. 1.
The pulse width data D0-D3 inputted over the data bus is temporarily stored in the register 1 and then applied to the comparison circuit 4. The external pulse width modulation enable signal PE as shown in FIG. 2A and the clock signal CK as shown in FIG. 2B are applied to the counting controller 2. When the external pulse width modulation enable signal PE and the clock signal CK are low, the counting controller 2 outputs the clock signal CK to the counter 3.
The counter 3 is operated under the control of the reset signal RE as shown in FIG. 2C. Namely, if the reset signal RE is high, the counter 3 counts the clock signal CK from the counting controller 2. On the contrary, if the reset signal RE is low, the counter 3 does not count the clock signal CK from the counting controller 2.
Then, the comparison circuit 4 compares the pulse width data D0-D3 from the register 1 as shown in FIG. 2D with the data Q0-Q3 from the counter 3 as shown in FIG. 2E. When the pulse width data D0-D3 from the register 1 is greater than the data Q0-Q3 from the counter 3, the comparison circuit 4 outputs a low signal to a reset terminal R of a flip-flop FF1 in the output unit 5. On the contrary, when the pulse width data D0-D3 from the register 1 is not greater than the data Q0-Q3 from the counter 3, the comparison circuit 4 outputs a high signal to the reset terminal S of the flip-flop FF1.
The signals applied to the set and reset terminals S and R are latched in the flip-flop FF1. As a result, the flip-flop FF1 outputs the pulse width modulation signal PWMO as shown in FIG. 2F in response to the signals latched therein.
For example, assume that the data Q0-Q3 from the counter 3 is hexa "0" and the pulse width data D0-D3 from the register 1 is hexa "5". In this case, logical low bits of the data Q0-Q3 of hexa "0" from the counter 3 are applied to exclusive-NOR gates XNOR1-XNOR4 of the comparison circuit 4. Also, logical high bits of the pulse width data D0-D3 of hexa "5" from the register 1 are applied to the exclusive-NOR gates XNOR1 and XNOR3 and logical low bits thereof are applied to the exclusive-NOR gates XNOR2 and XNOR4, Each of the exclusive-NOR gates XNOR1 and XNOR3 outputs a low signal because it inputs the high bit from the register 1 and the low bit from the counter 3. Each of the exclusive-NOR gates XNOR2 and XNOR4 outputs a high signal because it inputs the low bit from the register 1 and the low bit from the counter 3.
The low signals from the exclusive-NOR gates XNOR1 and XNOR3 and the high signals from the exclusive-NOR gates XNOR2 and XNOR4 are applied to a NAND gate NAND1 in the comparison circuit 4, thereby causing the NAND gate NAND1 to output a high signal.
Then, the high signal from the NAND gate NAND1 and the reset signal RE of high level as shown in FIG. 2C are applied to a NAND gate NAND2 in the comparison circuit 4, thereby causing the NAND gate NAND2 to output a low signal. The low signal from the NAND gate NAND2 is applied to the reset terminal R of the flip-flop FF1 in the output unit 5.
The logical low bits of the data Q0-Q3 of hexa "0" from the counter 3 are also applied to a NOR gate NOR1 in the comparison circuit 4, thereby causing the NOR gate NOR1 to output a high signal. The high signal from the NOR gate NOR1 is applied to the set terminal S of the flip-flop FF1 in the output unit 5.
As a result, the flip-flop FF1 outputs the pulse width modulation signal PWMO of high level as shown in FIG. 2F in response to the high and low signals applied respectively to the set and reset terminals S and R thereof.
Thereafter, when the counter 3 outputs the data Q0-Q3 of hexa "5" as it continues to count the clock signal CK from the counting controller 2, logical high bits of the data Q0-Q3 of hexa "5" from the counter 3 are applied to the exclusive-NOR gates XNOR1 and XNOR3 and logical low bits thereof are applied to the exclusive-NOR gates XNOR2 and XNOR4. Also, the logical high bits of the pulse width data D0-D3 of hexa "5" from the register 1 are applied to the exclusive-NOR gates XNOR1 and XNOR3 and the logical low bits thereof are applied to the exclusive-NOR gates XNOR2 and XNOR4. As a result, each of the exclusive-NOR gates XNOR1, XNOR2, XNOR3 and XNOR4 outputs a high signal.
The high signals from the exclusive-NOR gates XNOR1, XNOR2, XNOR3 and XNOR4 are applied to the NAND gate NAND1 in the comparison circuit 4, thereby causing the NAND gate NAND1 to output a low signal. The low signal from the NAND gate NAND1 is applied to the NAND gate NAND2 in the comparison circuit 4, which is also applied with the external reset signal RE of high level as shown in FIG. 2C. As a result, the NAND gate NAND2 outputs a high signal to the reset terminal R of the flip-flop FF1 in the output unit 5.
The logical low and high bits of the data Q0-Q3 of hexa "5" from the counter 3 are also applied to the NOR gate NOR1 in the comparison circuit 4, thereby causing the NOR gate NOR1 to output a low signal. The low signal from the NOR gate NOR1 is applied to the set terminal S of the flip-flop FF1 in the output unit 5.
As a result, the flip-flop FF1 outputs the pulse width modulation signal PWMO of low level as shown in FIG. 2F in response to the low and high signals applied respectively to the set and reset terminals S and R thereof.
With the above operation performed repeatedly, there can be obtained the pulse width modulation signal with a desired period and a desired width.
In other words, when the pulse width data D0-D3 from the register 1 is greater than the data Q0-Q3 from the counter 3, the conventional pulse width modulation apparatus outputs the pulse width modulation signal PWMO of high level. On the contrary, when the pulse width data D0-D3 from the register 1 is smaller than or equal to the data Q0-Q3 from the counter 3, the conventional pulse width modulation apparatus outputs the pulse width modulation signal PWMO of low level.
However, the above-mentioned conventional pulse width modulation apparatus has a disadvantage in that it outputs only one pulse every period, resulting in degradation in a frequency characteristic. Also, the use of a great number of devices like the NOR gate, the exclusive-NOR gates, the NAND gates and etc. reduces the data processing speed and the integration in manufacturing a single chip.